B222L Introduction to VHDL
Welcome to Victor's Mosaic Introduction to VHDL page
Latest Update 09 May 2012: Solutions to Past Paper Questions
Previous Update Update 30 April 2012: B222L - VHDL Revision Memory Map
Combinational Logic
Signals, concurrent statements, truth tables, logic, conditional signal assignment, data types, entities, architectures
Sequential Logic
Clocks, rising & falling edges, processes, sensitivity lists, sequential statements, current values, future values
VHDL Coursework Task
VHDL & CPLD Synthesis
Tutorial Sheets
Past Exam Papers
B222L this year has a revised syllabus so there are no VHDL questions on past B222L exam papers that match the revised syllabus
Below are example questions from past B122L papers from when an
Introduction to VHDL was part of the first year courses
Solutions...
Please look ONLY once you have had a go at the questions! Alternative solutions often exist for a particular problem
Xilinx ISE Tools
Capture, edit, syntax check, simulate, synthesis, generate, configure
...The ISE CPLD handout as separate chapters
Logbooks
A reminder about what should be in a logbook
Other Material
